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LTC4401-1/LTC4401-2 RF Power Controllers with 250kHz Loop BW and 45dB Dynamic Range
FEATURES
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DESCRIPTIO
TM
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RF Power Amplifier Control in ThinSOT Package Internal Schottky Diode Detector with > 45dB Range Wide Input Frequency Range: 300MHz to 2.7GHz (LTC4401-1) 300MHz to 2GHz (LTC4401-2) Autozero Loop Cancels Offset Errors and Temperature Dependent Offsets Wide VCC Range: 2.7V to 6V Automatic Bandwidth Control Improves Low Power Ramp Response Allows Direct Connection to Battery RF Output Power Set by External DAC Internal Frequency Compensation Rail-to-Rail Power Control Output Power Control Signal Overvoltage Protection Low Operating Current: 1mA Low Shutdown Current: 10A Two Pole PCTL Input Filtering Low Profile (1mm) SOT-23 (ThinSOTTM) (LTC4401-1) and 8-Pin MSOP (LTC4401-2) Packages
The LTC(R)4401-1 is a SOT-23 RF power controller for slow turn-on RF power amplifiers operating in the 300MHz to 2.7GHz range. The loop bandwidth is set at 250kHz to improve frequency stability when controlling slow turn-on RF power amplifiers such as the Conexant CX77301/CX77302, CX77304, CX77314, Anadigics AWT6107 and the RF Micro Devices RF3160. RF power is controlled by driving the RF amplifier power control pins and sensing the resultant RF output power via a directional coupler. The RF sense voltage is peak detected using an on-chip Schottky diode. This detected voltage is compared to the DAC voltage at the PCTL pin to control the output power. The RF power amplifier is protected against high power control pin voltages. Internal and external offsets are cancelled over temperature by an autozero control loop, allowing accurate low power programming. The shutdown feature disables the part and reduces the supply current to < 10A. A dual control channel version (LTC4401-2) is also available in an 8-pin MSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.
APPLICATIO S
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GSM/GPRS Cellular Telephones PCS Devices Wireless Data Modems U.S. TDMA Cellular Phones
TYPICAL APPLICATIO
LTC4401-1 Dual Band Cellular Telephone Transmitter
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33pF Li-Ion 0.1F 6 VCC LTC4401-1 SHDN 4 SHDN VPCA 5 VPC 900MHz INPUT 1.8GHz INPUT 900MHz OUTPUT RF 1 BAND SELECT
3 DAC
PCTL
GND
2
PA MODULE 1.8GHz OUTPUT 50
4401 TA01
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LTC4401-1/LTC4401-2
ABSOLUTE
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RATI GS
VCC to GND .............................................. - 0.3V to 6.5V VPCA/B Voltage to GND ............................ - 0.3V to 3.2V PCTL Voltage to GND ................. - 0.3V to (VCC + 0.3V) RF Voltage to GND ............................ (VCC - 2.6V) to 7V BSEL, SHDN Voltage to GND ...... - 0.3V to (VCC + 0.3V)
PACKAGE/ORDER I FOR ATIO
TOP VIEW RF 1 GND 2 PCTL 3 6 VCC 5 VPCA 4 SHDN
ORDER PART NUMBER LTC4401-1ES6 S6 PART MARKING LTXA
S6 PACKAGE 6-LEAD PLASTIC TSOT-23
TJMAX = 125C, JA = 230C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER VCC Operating Voltage IVCC Shutdown Current IVCC Operating Current VPCA/B VOL VPCA/B Dropout Voltage VPCA/B Voltage Clamp VPCA/B Output Current VPCA/B Enable Time VPCA/B Bandwidth VPCA/B Load Capacitance VPCA/B Slew Rate VPCA/B Droop VPCA/B Start Voltage BSEL, SHDN Input Threshold BSEL, SHDN Input Current PCTL Input Voltage Range PCTL Input Resistance PCTL Input Filter Autozero Range (Note 4) Open Loop (Note 9) VCC = 2.7V to 6V BSEL = SHDN = 3.6V (Note 7) SHDN = 0V SHDN = HI, IVPCA/B = 0mA RLOAD = 400, Enabled ILOAD = 6mA, VCC = 3V PCTL = 1V VPCA/B = 2.4V, VCC = 3V SHDN = VCC (Note 5) CONDITIONS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 3.6V, SHDN = HI, unless otherwise noted.
MIN
q q q q q q q q
CLOAD = 100pF, RLOAD = 2k (Note 8) (Note 6) VPCTL = 2V Step, CLOAD = 100pF, RLOAD = 400 (Note 3)
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(Note 1)
IVPCA/B .................................................................. 10mA Operating Temperature Range (Note 2) .. - 30C to 85C Storage Temperature Range ................ - 65C to 150C Maximum Junction Temperature ......................... 125C Lead Temperature (Soldering, 10 sec)................. 300C
TOP VIEW VCC VPCA VPCB GND 1 2 3 4 8 7 6 5 RF BSEL SHDN PCTL
ORDER PART NUMBER LTC4401-2EMS8 MS8 PART MARKING LTXC
MS8 PACKAGE 8-LEAD PLASTIC MSOP
TJMAX = 125C, JA = 250C/W
TYP 10 1.2
MAX 6 20 1.9 0.05 VCC - 0.25
UNITS V A mA V V V mA s kHz kHz pF V/s V/ms
2.7
0 2.7 7 175 2.9 10 9 250 130 1.5 1
3.1 10.2 330 100
PCTL < 80mV PCTL > 160mV
q q q
1
2
q q q q q
300 0.35 16 0 60
450 24 90 270
550 1.4 36 2.4 120 400
mV V A V k kHz mV
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LTC4401-1/LTC4401-2
ELECTRICAL CHARACTERISTICS
PARAMETER RF Input Frequency Range RF Input Power Range (LTC4401-1) CONDITIONS LTC4401-1 (Note 6) LTC4401-2 (Note 6)
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 3.6V, SHDN = HI, unless otherwise noted.
MIN 300 300 -28 -26 -24 -22 -28 -26
q
TYP
MAX 2700 2000 18 18 16 16 18 18
UNITS MHz MHz dBm dBm dBm dBm dBm dBm
RF Frequency = 900MHz (Note 6) RF Frequency = 1800MHz (Note 6) RF Frequency = 2400MHz (Note 6) RF Frequency = 2700MHz (Note 6) RF Frequency = 900MHz (Note 6) RF Frequency = 2000MHz (Note 6) Referenced to VCC
RF Input Power Range (LTC4401-2) RF Input Resistance
150
250
350
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC4401-X is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 30C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Slew rate is measured open loop. The slew time at VPCA/B is measured between 1V and 2V. Note 4: Maximum DAC zero-scale offset voltage that can be applied to PCTL.
Note 5: This is the time from SHDN rising edge 50% switch point to VPCA = 0.25V. Note 6: Guaranteed by design. This parameter is not production tested. Note 7: Includes maximum DAC offset voltage and maximum control voltage. Note 8: Bandwidth is calculated using the 10% to 90% rise time: BW = 0.35/rise time Note 9: Measured 12s after SHDN = HI.
TYPICAL PERFOR A CE CHARACTERISTICS
PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV) PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV) PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV)
LTC4401-1 Detector Characteristics at 900MHz
10000 75C 25C -30C
1000
100
10
1 -28
-22 -16 -10 -4 2 8 RF INPUT POWER (dBm)
UW
14
LTC4401-1 Detector Characteristics at 1800MHz
10000 75C 25C -30C
LTC4401-1 Detector Characteristics at 2400MHz
10000 75C 25C -30C
1000
1000
100
100
10
10
1 -26 -20
-14 -8 -2 4 10 RF INPUT POWER (dBm)
16
4401 G02
1 -24 -20 -16 -12 -8 -4 0 4 8 RF INPUT POWER (dBm)
12 16
4401 G03
4401 G01
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LTC4401-1/LTC4401-2 TYPICAL PERFOR A CE CHARACTERISTICS
PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV) PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV)
10000
10000
PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV)
LTC4401-1 Detector Characteristics at 2700MHz
75C 25C -30C
1000
100
10
1 -22 -18 -14 -10 -6 -2 2 6 RF INPUT POWER (dBm)
PI FU CTIO S
(LTC4401-1/LTC4401-2)
RF (Pins 1/8): RF Feedback Voltage from the Directional Coupler. Referenced to VCC. A coupling capacitor of 33pF must be used to connect to the ground referenced directional coupler. The frequency range is 300MHz to 2700MHz for the LTC4401-1 and 300MHz to 2000MHz for the LTC4401-2. This pin has an internal 250 termination, an internal Schottky diode detector and peak detector capacitor. GND (Pins 2/4): System Ground. PCTL (Pins 3/5): Analog Input. The external power control DAC drives this input. The amplifier servos the RF power until the RF detected signal equals the DAC signal. The input impedance is typically 90k. VPCB (Pin 3): (LTC4401-2 Only) Power Control Voltage Output. This pin drives an external RF power amplifier power control pin. The maximum load capacitance is 100pF.
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LTC4401-2 Detector Characteristics at 900MHz
75C 25C -30C
LTC4401-2 Detector Characteristics at 1800MHz
10000 75C 25C -30C
1000
1000
100
100
10
10
10 14
4401 G04
1 -28
-22 -16 -10 -4 2 8 RF INPUT POWER (dBm)
14
4401 G05
1 -26 -20
-14 -8 -2 4 10 RF INPUT POWER (dBm)
16
4401 G06
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SHDN (Pins 4/6): Shutdown Input. A logic low on the SHDN pin places the part in shutdown mode. A logic high places the part in enable mode. SHDN has an internal 150k pulldown resistor to ensure that the part is in shutdown when the drivers are in a three-state condition. VPCA (Pins 5/2): Power Control Voltage Output. This pin drives an external RF power amplifier power control pin. The maximum load capacitance is 100pF. VCC (Pins 6/1): Input Supply Voltage, 2.7V to 6V. VCC should be bypassed with 0.1F and 100pF ceramic capacitors. Used as return for RF 250 termination. BSEL (Pin 7): (LTC4401-2 Only) Selects VPCA when Low and VPCB when High. This input has an internal 150k resistor to ground.
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LTC4401-1/LTC4401-2
BLOCK DIAGRA
68
33pF VCC 6
250 RF 1
28pF 30k 60A GND 2 60A
VBG
VREF
W
30k
(LTC4401-1)
RF IN
RF PA
50
Li-Ion
TXENB AUTOZERO
-
AZ
+ +
GAIN COMPRESSION
-
GM
+ + -
80mV 270kHz FILTER
CLAMP
+
CC BUFFER 5
+
RF DET
38k
-
30k 30k
VPCA
-
22k 51k VREF
+ -
33.4k
6k 12
TXENB 10s DELAY 150k LTC4401-1 4 SHDN 3
4401-1 BD
CONTROL
100
PCTL
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LTC4401-1/LTC4401-2
BLOCK DIAGRA W
+
RF DET
(LTC4401-2)
DIPLEXER
68
900MHZ 33pF VCC 1
RF PA 50
RF PA
1.8GHz/1.9GHz
Li-Ion
TXENB AUTOZERO
-
AZ
+ +
GAIN COMPRESSION 250 RF 8
-
GM BUF A CLAMP 2
+ + -
30k 80mV 270kHz FILTER 38k
VPCA
+
CC
MUX1
MUX2
-
30k 30k 12
28pF 30k 60A GND 4 60A
-
22k 51k VREF
+ -
BUF B
3
VPCB
33.4k
6k
100
TXENB VBG VREF 10s DELAY 150k 150k CONTROL
12 VPCA 100
LTC4401-2 6 SHDN 5 PCTL 7
4401-2 BD
BSEL
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LTC4401-1/LTC4401-2
APPLICATIONS INFORMATION
Operation The LTC4401-X RF power control amplifier integrates several functions to provide RF power control over frequencies ranging from 300MHz to 2.7GHz. This product is well suited to control RF power amplifiers that exhibit slow turn-on times. The device also prevents damage to the RF power amplifier due to overvoltage conditions. These functions include an internally compensated power control amplifier to control the RF output power, an autozero section to cancel internal and external voltage offsets, an RF Schottky diode peak detector and amplifier to convert the RF feedback signal to DC, a VPCA/B overvoltage clamp, compression and a bandgap reference. Band Selection The LTC4401-2 is designed to drive two separate power control lines. The BSEL pin will select VPCA when low and VPCB when high. BSEL must be established prior to SHDN being asserted high. Control Amplifier The control amplifier supplies the power control voltage to the RF power amplifier. A portion (typically - 19dB for low frequencies and -14dB for high frequencies) of the RF output voltage is sampled, via a directional coupler, to close the gain control loop. When a DAC voltage is applied to PCTL, the amplifier quickly servos VPCA/B positive until the detected feedback voltage applied to the RF pin matches the voltage at PCTL. This feedback loop provides accurate RF power control. VPCA/B is capable of driving a 6mA load current and 100pF load capacitor. Control Amplifier Compression The gain compression breakpoints are at PCTL = 80mV and PCTL = 160mV. Above 160mV the gain does not change. The compression changes the feedback attenuation thereby reducing the loop gain. RF Detector The internal RF Schottky diode peak detector and amplifier converts the RF feedback voltage from the directional coupler to a low frequency voltage. This voltage is compared to the DAC voltage at the PCTL pin by the control amplifier to close the RF power control loop. The RF pin input resistance is typically 250 and the frequency range of this pin is 300MHz to 2700MHz for the LTC4401-1 and 300MHz to 2000MHz for the LTC4401-2. The detector demonstrates excellent efficiency over a wide range of input power. The Schottky detector is biased at about 60A and drives an on-chip peak detector capacitor of 28pF. Autozero An autozero system is included to improve power programming accuracy over temperature. This section cancels internal offsets associated with the Schottky diode detector and control amplifier. External offsets associated with the DAC driving the PCTL pin are also cancelled. Offset drift due to temperature is cancelled between each burst. The maximum offset voltage allowed at the DAC output is limited to 400mV. Autozeroing is performed during a 10s period after SHDN is asserted high. An internal timer enables the VPCA/B output after 10s. The autozero capacitors are held and the VPCA/B pin is connected to the control amplifier output. The hold droop voltage of typically < 1V/ms provides for accurate offset cancellation. The part should be shut down between bursts or after multiple consecutive bursts. Filter There is a 270kHz two pole filter included in the PCTL path to remove DAC noise. Protection Features The RF power amplifier control voltage pin is overvoltage protected. The VPCA/B overvoltage clamp regulates VPCA/B to 2.9V when the gain and PCTL input combination attempts to exceed this voltage. Modes of Operation Shutdown: The part is in shutdown mode when SHDN is low. VPCA/B is held at ground and the power supply current is typically 10A.
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LTC4401-1/LTC4401-2
APPLICATIO S I FOR ATIO
Enable: When SHDN is asserted high the part will automatically calibrate out all offsets. This takes <10s and is controlled by an internal delay circuit. After 10s VPCA/B will step up to the starting voltage of 450mV. The user can then apply the ramp signal. The user should wait 12s after SHDN has been asserted high before applying the ramp. The DAC should be settled 2s after asserting SHDN high.
LTC4401-X Timing Diagram
T7 BSEL (LTC4401-2 ONLY) 2s 10s SHDN 28s 543s 28s T8
VPCA/B VSTART PCTL
4400 TA02
T1
T2 T3
T4
T5
T1: LTC4401-X COMES OUT OF SHUTDOWN 12s PRIOR TO BURST T2: INTERNAL TIMER COMPLETES AUTOZERO CORRECTION, <10s T3: BASEBAND CONTROLLER STARTS RF POWER RAMP UP AT 12s AFTER SHDN IS ASSERTED HIGH T4: BASEBAND CONTROLLER COMPLETES RAMP UP T5: BASEBAND CONTROLLER STARTS RF POWER RAMP DOWN AT END OF BURST T6: LTC4401-X RETURNS TO SHUTDOWN MODE BETWEEN BURSTS T7: BSEL CHANGE PRIOR TO SHDN, 0ns TYPICAL (LTC4401-2 ONLY) T8: BSEL CHANGE AFTER TO SHDN, 0ns TYPICAL (LTC4401-2 ONLY)
General Layout Considerations The LTC4401-X should be placed near the directional coupler. The feedback signal line to the RF pin should be a 50 transmission line with optional termination or a short line. External Termination The LTC4401-X has an internal 250 termination resistor at the RF pin. If a directional coupler is used, it is recommended that an external 68 termination resistor be connected between the RF coupling capacitor (33pF), and ground at the side connected to the directional coupler. Termination components should be placed adjacent to the LTC4401-X.
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Power Ramp Profiles The external voltage gain associated with the RF channel can vary significantly between RF power amplifier types. The LTC4401-X frequency compensation has been optimized to be stable with several different power amplifiers and manufacturers. This frequency compensation generally defines the loop dynamics that impact the power/ time response and possibly (slow loops) the power ramp sidebands. The LTC4401-X operates open loop until an RF voltage appears at the RF pin, at which time the loop closes and the output power follows the DAC profile. The RF power amplifier will require a certain control voltage level (threshold) before an RF output signal is produced. The LTC4401-X VPCA/B output(s) must quickly rise to this threshold voltage in order to meet the power/time profile. To reduce this time, the LTC4401-X starts at 450mV. However, at very low power levels the PCTL input signal is small, and the VPCA/B output may take several microseconds to reach the RF power amplifier threshold voltage. To reduce this time, it may be necessary to apply a positive pulse at the start of the ramp to quickly bring the VPCA/B output to the threshold voltage. This can generally be achieved with DAC programming. The magnitude of the pulse is dependent on the RF amplifier characteristics. Power ramp sidebands and power/time are also a factor when ramping to zero power. When the power is ramped down the loop will eventually open at power levels below the LTC4401-X detector threshold. The LTC4401-X will then go open loop and the output voltage at VPCA/B will stop falling. If this voltage is high enough to produce RF output power, the power/time or power ramp sidebands may not meet specification. This problem can be avoided by starting the DAC ramp from 200mV (Figure 1). At the end of the cycle, the DAC can be ramped down to 0mV. This applies a negative signal to the LTC4401-X thereby ensuring that the VPCA/B output will ramp to 0V. The 200mV ramp step must be applied < 2s after SHDN is asserted high to allow the autozero to cancel the step. Slow DAC rise times will extend this time by the additional RC time constants which may require that the DAC is enabled and settled prior to SHDN asserted high.
T6
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LTC4401-1/LTC4401-2
APPLICATIO S I FOR ATIO
10 0 -10
RFOUT (dBc)
-20 -30 -40 -50 -60 -70 -80 -28 -18 -10 0 TIME (s) 543 553 561 571
DAC VOLTAGE
START PULSE START CODE ZERO CODE
200mV
SHDN 12s, ALLOWS TIME FOR DAC AND AUTOZERO TO SETTLE
4401 F01
Figure 1. LTC4401-X Ramp Timing
Demo Board The LTC4401-X demo board is available upon request. The demo board has a 900MHz and an 1800MHz RF channel controlled by the LTC4401-X. Timing signals for SHDN are generated on the board using a 13MHz crystal reference. The PCTL power control pin is driven by a 10-bit DAC and the DAC profile can be loaded via a serial port. The serial port data is stored in a flash memory which is capable of storing eight ramp profiles. The board is supplied preloaded with four GSM power profiles and four DCS power profiles covering the entire power range. External timing signals can be used in place of the internal crystal controlled timing. A variety of RF power amplifiers as well as ramp generation software are available. LTC4401-X Control Loop Stability The LTC4401-X provides a stable control loop for several RF power amplifier models from different manufacturers over a wide range of frequencies, output power levels and VSWR conditions. However, there are several factors that can improve or degrade loop frequency stability.
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1) The additional voltage gain supplied by the RF power amplifier increases the loop gain raising poles normally below the 0dB axis. The extra voltage gain can vary significantly over input/output power ranges, frequency, power supply, temperature and manufacturer. RF power amplifier gain control transfer functions are often not available and must be generated by the user. Loop oscillations are most likely to occur in the midpower range where the external voltage gain associated with the RF power amplifier typically peaks. It is useful to measure the oscillation or ringing frequency to determine whether it corresponds to the expected loop bandwidth and thus is due to high gain bandwidth. 2) Loop voltage losses supplied by the directional coupler will improve phase margin. The larger the directional coupler loss the more stable the loop will become. However, larger losses reduce the RF signal to the LTC4401-X and detector performance may be degraded at low power levels. (See RF Detector Characteristics.) 3) Additional poles within the loop due to filtering or the turn-on response of the RF power amplifier can degrade the phase margin if these pole frequencies are near the effective loop bandwidth frequency. Generally loops using RF power amplifiers with fast turn-on times have more phase margin. Extra filtering below 16MHz should never be placed within the control loop, as this will only degrade phase margin. 4) Control loop instability can also be due to open-loop issues. RF power amplifiers should first be characterized in an open-loop configuration to ensure self oscillation is not present. Self-oscillation is often related to poor power supply decoupling, ground loops, coupling due to poor layout and extreme VSWR conditions. The oscillation frequency is generally in the 100kHz to 10MHz range. Power supply related oscillation suppression requires large value ceramic decoupling capacitors placed close to the RF power amp supply pins. The range of decoupling capacitor values is typically 1nF to 3.3F. 5) Poor layout techniques associated with the directional coupler area may result in high frequency signals bypassing the coupler. This could result in stability problems due to the reduction in the coupler loss.
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LTC4401-1/LTC4401-2
APPLICATIO S I FOR ATIO
Determining External Loop Gain and Bandwidth The external loop voltage gain contributed by the RF channel and directional coupler network should be measured in a closed-loop configuration. A voltage step is applied to PCTL and the change in VPCA/B is measured. The detected voltage is K * PCTL, where K is the internal gain between PCTL and the RF pin, and the external voltage gain contributed by the RF power amplifier and directional coupler network is K * VPCTL/VVPC. Measuring voltage gain in the closed-loop configuration accounts for the nonlinear detector gain that is dependent on RF input voltage and frequency. The LTC4401-X unity gain bandwidth specified in the data sheet assumes that the net voltage gain contributed by the RF power amplifier and directional coupler is unity. The bandwidth is calculated by measuring the rise time between 10% and 90% of the voltage change at VPCA/B for a small step in voltage applied to PCTL. BW1 = 0.35/rise time The LTC4401-X control amplifier unity gain bandwidth (BW1) is typically 250kHz below a PCTL voltage of 80mV. For PCTL voltages < 80mV, the RF detected voltage is 0.6PCTL. For PCTL voltages >160mV, RF detected voltage is 1.22PCTL - 0.1. This change in gain is due to an internal compression circuit designed to extend the detector range. For example, to determine the external RF channel loop voltage gain with the loop closed, apply a 100mV step to
80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 -50 -60 100 160 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 10M
PHASE
RLOAD = 2k CLOAD = 33pF PCTL = 60mV
VOLTAGE GAIN (dB)
VOLTAGE GAIN (dB)
GAIN
1k
10k 100k FREQUENCY (Hz)
1M
4401 F02
Figure 2. Measured Open-Loop Gain and Phase, PCTL < 80mV
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PCTL from 300mV to 400mV. VPCA/B will increase to supply enough feedback voltage to the RF pin to cancel this 100mV step which would be the required detected voltage step of 122mV. VPCA/B changed from 1.5V to 1.561V to create the RF output power change required. The net external voltage gain contributed by the RF power amplifier and directional coupler network can be calculated by dividing the 122mV change at the RF pin by the 61mV change at the VPCA/B pin. The net external voltage gain would then be approximately 2. The loop bandwidth extends to 2 * BW1. If BW1 is 130kHz, the loop bandwidth increases to approximately 260kHz. The phase margin can be determined from Figures 2 and 3. Repeat the above voltage gain measurement over the full power and frequency range. External pole frequencies within the loop will further reduce phase margin. The phase margin degradation, due to external and internal pole combinations, is difficult to determine since complex poles are present. Gain peaking may occur, resulting in higher bandwidth and lower phase margin than predicted from the open-loop Bode plot. A low frequency AC SPICE model of the LTC4401-X power controller is included to better determine pole and zero interactions. The user can apply external gains and poles to determine bandwidth and phase margin. DC, transient and RF information cannot be extracted from the present model. The model is suitable for external gain evaluations up to 6 x. The 270kHz PCTL input filter limits the bandwidth, therefore, use the RF input as demonstrated in the model. Gain compression is not modeled.
80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 -50 -60 100 RLOAD = 2k CLOAD = 33pF PHASE 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 10M
PHASE (DEG) PHASE (DEG)
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GAIN
1k
10k 100k FREQUENCY (Hz)
1M
4401 F03
Figure 3. Measured Open-Loop Gain and Phase, PCTL > 160mV
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LTC4401-1/LTC4401-2
APPLICATIO S I FOR ATIO
This model (Figure 6) is being supplied to LTC users as an aid to circuit designs. While the model reflects reasonably close similarity to corresponding devices in low frequency AC performance terms, its use is not suggested as a replacement for breadboarding. Simulation should be used as a forerunner or a supplement to traditional lab testing. Users should note very carefully the following factors regarding this model: Model performance in general will reflect typical baseline specs for a given device, and certain aspects of performance may not be modeled fully. While reasonable care has been taken in the preparation, we cannot be responsible for correct application on any and all computer systems. Model users are hereby notified that these models are supplied "as is", with no direct or implied responsibility on the part of LTC for their operation within a customer circuit or system. Further, Linear Technology Corporation reserves the right to change these models without prior notice. In all cases, the current data sheet information is your final design guideline, and is the only performance guarantee. For further technical information, refer to individual device data sheets. Your feedback and suggestions on this model is appreciated.
CONTROL AMPLIFER RF POWER AMP VPC G1 G2 CONTROLLED RF OUTPUT POWER
VOLTAGE GAIN (dB)
+
PCTL
-
IFB LTC4401-X H1 RF H2
4401 F04
RF DETECTOR
DIRECTIONAL COUPLER 14dB to 20dB LOSS
Figure 4. Closed-Loop Block Diagram
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Linear Technology Corporation hereby grants the users of this model a nonexclusive, nontransferable license to use this model under the following conditions: The user agrees that this model is licensed from Linear Technology and agrees that the model may be used, loaned, given away or included in other model libraries as long as this notice and the model in its entirety and unchanged is included. No right to make derivative works or modifications to the model is granted hereby. All such rights are reserved. This model is provided as is. Linear Technology makes no warranty, either expressed or implied about the suitability or fitness of this model for any particular purpose. In no event will Linear Technology be liable for special, collateral, incidental or consequential damages in connection with or arising out of the use of this model. It should be remembered that models are a simplification of the actual circuit.
80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 -50 -60 100 180 RLOAD = 2k 160 CLOAD = 33pF 140 120 PHASE 100 80 60 GAIN 40 20 0 -20 -40 -60 -80 -100 10k 100k 1M 10M FREQUENCY (Hz)
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PHASE (DEG)
1k
Figure 5. SPICE Model Open-Loop Gain and Phase Characteristics from RF to VPCA, PCTL < 80mV
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LTC4401-1/LTC4401-2
APPLICATIO S I FOR ATIO
*LTC4401-X Low Frequency AC Spice Model* *July 11, 2001 *Main Network Description GGIN1 ND3 0 ND2 IFB 86E-6 GGXFB IFB 0 0 ND12 33E-6 GGX5 ND11 0 0 ND10 1E-6 GGX6 ND12 0 0 ND11 1E-6 GGX1 ND4 0 0 ND3 1E-6 GGX2 ND6 0 0 ND4 1E-6 GGX3 ND7 0 0 ND6 1E-6 GGX4 ND8 0 0 ND7 1E-6 EEX1 ND9 0 0 ND8 2 CCC1 ND3 0 75E-12 CCPCTL2 ND2 0 7E-12 CCPCTL1 ND1 0 13E-12 CCLINT VPCA 0 5E-12 CCLOAD VPCA 0 33E-12 CCFB1 IFB 0 2.4E-12 CCX5 ND11 0 16E-15 CCX6 ND12 0 1.2E-15 CCP ND10 0 28E-12 CCX2 ND6 0 8E-15 CCX3 ND7 0 32E-15 LLX1 ND5 0 65E-3 RR01 ND3 0 20E6 RRFILT ND2 ND1 44E3 RRPCTL1 PCTL ND1 51E3 RRPCTL2 ND1 0 38E3 RR9 VPCA ND9 50 RRLOAD VPCA 0 2E3 RRFB1 IFB 0 22E3 RRT RF 0 250 RRX5 ND11 0 1E6 RRX6 ND12 0 1E6 RRSDRF ND10 500 RRX1 ND4 ND5 1E6 RRX2 ND6 0 1E6 RRX3 ND7 0 1E6 RRX4 ND8 0 1E6 **Closed-loop feedback, comment-out VPCTLO, VRF, Adjust EFB gain to reflect external gain, currently set at 3X** *EFB RF 0 VPCA VIN 3 *VIN VIN 0 DC 0 AC 1 *VPCTLO PCTL 0 DC 0 **Open-loop connections, comment-out EFB, VIN and VPCTLO****** VPCTLO PCTL 0 DC 0 VRF RF 0 DC 0 AC 1 ******Add AC statement and print statement as required*** .AC DEC 50 100 1E7 *****for PSPICE only***** .OP .PROBE ************************* .END
Figure 6. LTC4401-X Low Frequency AC SPICE Model
4401fa
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U
W
UU
LTC4401-1/LTC4401-2
APPLICATIO S I FOR ATIO
PCTL RPCTL1 51E3 ND1 RFILT 44E3 ND2 ND3
+
GM
GIN1 RO1 20E6 86E-6 CC1 75E-12
+
GM
CPCTL1 13E-12
RPCTL2 38E3 C PCTL2 7E-12
-
-
RF RT 250 RSD 500 ND10 CP 28E-12
ND11
+
GM
GX5 RX5 1E6 1E-6 CX5 16E-15
+
GM
GX6 RX6 1E6 1E-6 CX6 1.2E-15
-
-
Figure 7. LTC4401-X Low Frequency AC Model
U
ND4 GX1 RX1 1E6 ND5 LX1 65E-3 ND6 ND7 ND8
W
UU
+
GM
GX2 RX2 1E6 1E-6 CX2 8E-15
+
GM
GX3 RX3 1E6 1E-6 CX3 32E-15
+
GM
GX4 RX4 1E6 1E-6
1E-6
-
-
-
IFB
ND8
2X BUFFER ND12 GXFB GM RFB1 22E3 33E-6 CFB1 2.4E-12 EX1 VAMP
+ -
+ -
2
R9 50 CLINT 5E-12
ND9 RLOAD 2E3
VPCA CLOAD 33E-12
4401 F07
4401fa
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LTC4401-1/LTC4401-2
PACKAGE DESCRIPTIO
0.62 MAX
0.95 REF
3.85 MAX 2.62 REF
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.20 BSC 1.00 MAX DATUM `A'
0.30 - 0.50 REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 0.09 - 0.20 (NOTE 3)
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U
S6 Package 6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC (NOTE 4) 1.22 REF 1.4 MIN 2.80 BSC 1.50 - 1.75 (NOTE 4) PIN ONE ID 0.95 BSC 0.30 - 0.45 6 PLCS (NOTE 3) 0.80 - 0.90 0.01 - 0.10 1.90 BSC
S6 TSOT-23 0302
4401fa
LTC4401-1/LTC4401-2
PACKAGE DESCRIPTIO U
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 0.127 (.035 .005) 3.20 - 3.45 (.126 - .136) 0.65 (.0256) BSC 3.00 0.102 (.118 .004) (NOTE 3) 8 7 65 0.52 (.0205) REF DETAIL "A" 0 - 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 0.127 0.076 (.005 .003)
MSOP (MS8) 0204
5.23 (.206) MIN
0.42 0.038 (.0165 .0015) TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
1 1.10 (.043) MAX
23
4 0.86 (.034) REF
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.65 (.0256) BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC4401-1/LTC4401-2
TYPICAL APPLICATION
LTC4401-2 Dual Band Cellular Telephone Transmitter
68 33pF RF VPCA VPCB PCTL 50 DAC 1.8GHz/ 1.9GHz RF PA 900MHz RF PA DIRECTIONAL COUPLER
VIN Li-Ion SHDN BSEL 0.1F
RELATED PARTS
PART NUMBER LTC1503 LTC1555L-1.8 LT 1615 LT1617 LTC1682 LTC1734 LT1761 LTC1878 LTC1911 LTC1928 LT1932 LT1944 LTC1986 LTC3200 LTC3202 LTC3401 LTC3402 LTC3404 LTC3405 LTC4400 LTC5505
(R)
DESCRIPTION Inductorless Step-Down DC/DC Converter SIM Power Supply and Level Translator Step-Up DC/DC Converter Inverting DC/DC Converter Low Noise Charge Pump with LDO SOT-23 Li-Ion Battery Charger Low Dropout, Low Noise Linear Regulator Step-Down DC/DC Converter Low Noise, Inductorless Buck Controller Low Noise Charge Pump White LED Driver Step-Up DC/DC Converter SIM Power Supply Low Noise Charge Pump Charge Pump for White LED Step-Up DC/DC Converter Step-Up DC/DC Converter Step-Down DC/DC Converter 1.5MHz, 250mA ThinSOT Buck Converter RF Power Controller in ThinSOT RF Power Detector in ThinSOT
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
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LTC4401-2 VCC SHDN BSEL GND
DIPLEXER
4401 TA03
COMMENTS 600kHz, Up to 100mA, 25% Higher Efficiency Than Linear Regulator Generates 1.8V, 3V or 5V; >10kV ESD on All SIM Contact Pins ThinSOT, Low 20A Quiescent Current, VIN as Low as 1V, 300mA IOUT ThinSOT, Low 20A Quiescent Current, VIN as Low as 1V, 300mA IOUT 60VRMS Output Noise, Small MSOP Package Up to 700mA Charge Current, Only Two External Components ThinSOT, 300mV Dropout at 100mA, 20VRMS Output Noise (10Hz to 100kHz) Integrated Synchronous Operation, Up to 95% Efficiency, 1A Switch Current. 2.7V VIN 5.5V, IOUT 250mA, 1.5MHz, 8-Pin MSOP ThinSOT, 90VRMS Output Noise (100kHz BW), IOUT Up to 30mA ThinSOT, 1.2MHz DC/DC Constant-Current LED Driver, Dimming Control Dual Output for LCD Bias, Low Quiescent Current of 20A, 1.2V VIN 15V ThinSOT, 3V and 5V, Ultralow Supply Current of 14A, <0.92cm2 PCB 2MHz Switching Frequency Allows Small Size Capacitors, IOUT Up to 100mA 2.5% Less Input Current than Doubler Charge Pump, IOUT 125mA Synchronous Rectification, Up to 97% Efficiency, 1A Switch Current, 3MHz Synchronous Rectification, Up to 97% Efficiency, 2A Switch Current, 3MHz 1.4MHz Synchronous Rectification, 10A Quiescent Current Up to 96% Efficiency, 2.5V VIN 5.5V, No Schottky Diode 450kHz Loop BW and 45dB Dynamic Range >40dB Dynamic Range, 300MHz to 3GHz, Buffered Detector Output
4401fa LT/TP 0204 1K REV A * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

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